Field
Embodiments of the present invention generally relate to methods for removing gate residuals in a gate structure, and more particularly to methods for removing gate electrode residuals in a gate structure from a substrate after features are formed in a gate electrode layer for semiconductor manufacturing applications.
Description of the Related Art
Reliably producing sub-half micron and smaller features is one of the key technology challenges for next generation very large scale integration (VLSI) and ultra large-scale integration (ULSI) of semiconductor devices. However, as the limits of circuit technology are pushed, the shrinking dimensions of VLSI and ULSI technology have placed additional demands on processing capabilities. Reliable formation of gate structures on the substrate is important to VLSI and ULSI success and to the continued effort to increase circuit density and quality of individual substrates and die.
As circuit densities increase for next generation devices, the widths of interconnects, such as vias, trenches, contacts, gate structures and other features, as well as the dielectric materials therebetween, decrease to 45 nm and 32 nm dimensions, whereas the thickness of the dielectric layers remain substantially constant, with the result of increasing the aspect ratios of the features. In order to enable fabrication of next generation devices and structures, three dimensional (3D) stacking of semiconductor chips is often utilized to improve performance of the transistors. By arranging transistors in three dimensions instead of conventional two dimensions, multiple transistors may be placed in the integrated circuits (ICs) very close to each other. Three dimensional (3D) stacking of semiconductor chips reduces wire lengths and keeps wiring delay low. In manufacturing three dimensional (3D) stacking of semiconductor chips, stair-like structures are often utilized to allow multiple interconnection structures to be disposed thereon, forming high-density of vertical transistor devices.
When forming features, such as trenches or vias, in stair-like structures or gate structures in a film stack disposed on a substrate, an etch process using a photoresist layer as an etching mask is often utilized. In gate structures, a gate electrode is formed over a gate dielectric with high aspect ratios. Typically, conventional etchants have low selectivity to etch gate electrode materials over other materials present in the gate structure, such as gate dielectric and/or underlying materials, thereby leaving void space, also known as silicon recess, foot, or other associated defects on the interface of the gate electrode over the gate dielectric or other materials. The gate electrode foot effect may become severe when etching features into the gate electrode material with high aspect ratio, resulting in higher amount of gate electrode material residuals left on sidewalls, corners, or bottom the substrate surface.
Thus, the etch selectivity for the gate electrode layer (e.g., polysilicon and silicon materials) to other materials on the gate structures, such as silicon oxide or silicon nitride, has to be very high in order to protect or passivate the sidewall of the gate electrode layer or the surface of the underlying gate structure.
Thus, there is a need for improved methods for etching or removing gate electrode with minimum defects and residuals for gate structures at semiconductor chip manufacture applications or other semiconductor devices.